The present invention relates to a fail-safe apparatus for counting enumeration input pulses. More particularly, the present invention relates to a fail-safe counting apparatus in which counting is completed after a predetermined time from the point of receipt of a counting instruction. The counting apparatus of the present invention can be utilized as a fail-safe timer for stopping or starting buzzer sounding after the lapse of a predetermined time, for example, in a crossing alarm signal apparatus.
For example, in the crossing alarm signal apparatus, a bell or buzzer is sounded while a train is passing through a railway crossing. Starting of buzzer sounding should not be delayed by any errors and stopping of buzzer sounding should not be quickened by any errors. In order to satisfy this requirement, a fail-safe counting apparatus for counting a predetermined time after receipt of a counting instruction becomes necessary.
A counting apparatus of this type has already been proposed by us in Japanese Patent Application Laid-Open Specification No. 41702/82. In this proposal, there is used a memory device indicating an asymmetrical error mode, in which an output voltage is reduced to zero when a failure takes place in a circuit. In this memory device, enumeration input signals having positive and negative polarities and reset signals in which the voltage is set at OV whenever they are reset by a polar voltage are used as the input signals. The memory device comprises steering gate circuits consisting of an asymmetrical error logic circuit producing an output voltage on receipt of the enumeration input signal, and output of the respective steering gate circuits are put as set signals in respective memory circuits.
In this prior technique, since there are disposed steering circuits and ternary inputs are necessary, the circuit structure is complicated.